This invention relates to digital phase-locked loops for synchronizing a local clock signal to a received digital signal with minimum jitter.
In general, phase-locked loops include an error (phase) detector for receiving an incoming digital signal, a low pass filter, a voltage controlled oscillator, and a feedback circuit, such as a divider circuit, for directing the output signal from the voltage controlled oscillator back to an input to the error detector as a reference signal for a comparison against the incoming digital signal. If the phase relationship between the digital signal and the reference signal changes, the error detector provides an error signal indicative of the direction and the magnitude of the change. The output of the voltage controlled oscillator is then adjusted in response to a filtered version of the error signal to drive the error signal to zero to lock the reference signal derived from the voltage controlled oscillator to the incoming digital signal.
One patent of particular interest is U.S. Pat. No. 3,781,695 entitled, "Digital Phase-Locked-Loop, by E. J. Jackson. The circuit of that patent uses an up-down counter to produce a resultant count signal that is proportioned to the lead or the lag of the phase difference between a reference signal and the incoming signal. The resultant count signal is used to adjust the reference signal so as to lock the reference signal to the incoming signal.
The deviation of the reference signal, in most phase-lock loop systems, can be either positive (high) or negative (low) with respect to the incoming signal. Two sets of circuits are used to provide the needed correction. One circuit processes deviations which are positive and the other circuit processes deviations which are negative. Although each set of circuits may contain identical circuit components, there are enough differences in the electrical characteristics of the components that identical signals applied to each correction circuit will produce a different output. When such a system is used in an environment requiring minimum jitter, in the output signal, the requirement is not met because the reference signal is continually driven positive and negative in an uneven manner around the desired null position. This continual hunting around the null position is called jitter.
The present invention is directed to a system for minimizing that jitter.